The invention relates generally to methods and apparatus for fabricating dynamic random access memory circuits (DRAMs). More particularly, the invention relates to methods and apparatus for controlling the amount of dopant outdiffusion from a DRAM trench capacitor into drains or gates of adjacent transistors in a DRAM.
In the fabrication of a DRAM, many high temperature, e.g., anneal, steps may be employed. By way of example, such high temperature steps may be employed to heal dislocations, reflow dielectrics, and/or to activate doped junctions. The high temperature steps may, however, cause an undue amount of dopants to diffuse from the underlying doped polysilicon layer of the trench capacitor into an adjacent drain or source of the transistor coupled to that capacitor. This undue diffusion may occur through a buried strap structure, i.e., the structure employed to connect the underlying doped polysilicon with the drain/source region of the transistor.
To facilitate discussion, FIG. 1 is a diagrammatic (and not to scale) representation of a portion of a DRAM circuit, including trench capacitor 100 and transistor 102. A buried strap structure 104 is provided to electrically couple underlying doped polysilicon region 106 with a doped junction region 108 of transistor 102 in the final DRAM cell structure. Doped junction region 108 may represent, for example, either a drain or a source of transistor 102.
Roughly speaking, trench capacitor 100 is formed by first forming a trench within silicon substrate 110 and then conformally deposit a dielectric layer 112 into the trench. Dielectric layer 112, which may be an oxide (SiO.sub.2), nitride (Si.sub.x N.sub.y), oxynitride (SiN.sub.x O.sub.y), or a combination of films, electrically insulates a subsequently deposited doped polysilicon layer 114 (e.g., phosphorous-doped polysilicon layer) from the substrate.
Thereafter, the trench is etched again to recess the polysilicon layer in the trench. An insulating material (e.g., silicon dioxide) is then deposited and etched to form an insulating spacer 116. Thereafter, another doped polysilicon layer (which may be similarly doped as polysilicon layer 104) is deposited within spacer 116 inside the trench. This doped polysilicon layer is then etched back to form the aforementioned doped polysilicon region 106. Buried strap structure 104, which may be intrinsic (i.e., undoped) or lightly doped polysilicon, is then formed above doped polysilicon region 106. The buried strap 104 may be formed by the deposition, planarization, and recess etch of a deposited polysilicon material.
During the subsequent high temperature steps, some of the dopants from underlying polysilicon region 106 are driven into buried strap 104, thereby lowering the resistance of buried strap 104. As can be seen in FIG. 1, the outdiffusion of dopants into buried strap 104 forms an electrical path between doped junction region 108 of transistor 102 and doped polysilicon region 114 of trench capacitor 100 through buried strap 104 and doped polysilicon region 106.
It has been found, however, that the aforementioned high temperature steps may cause an undue amount of dopants from underlying polysilicon region 106 to diffuse into doped junction region 108 through buried strap 104. This excessive dopant contamination of the doped junction regions generally detrimentally affects the performance of the associated transistor 102 (which includes the doped junction regions). Hence, high temperature steps are often limited in the prior art to reduce the amount of dopant outdiffusion into doped junction region 108. That is, the thermal budget of integrated circuit fabrication processes may be limited in order to reduce contamination.
Reducing the thermal budget of an integrated circuit fabrication process, while generally effective in reducing contamination of doped junction regions, often proves to be undesirable. For example, when the thermal budget is reduced, some high temperature steps, i.e., steps which occur at temperatures greater than about 900 degrees Centigrade, may be shortened. As mentioned, such steps are typically necessary to heal dislocations, reflow dielectrics, and to activate doped junctions, for example. Shortening these steps therefore compromises the structural integrity of the final IC. Further, for DRAMS, reducing the number of dislocations which may be healed generally significantly increases the retention time associated with the DRAM by decreasing device leakage. As the term is used herein, retention time refers to the time a DRAM cell retains its stored charge, and is typically limited by the rate at which the stored charge leaks away.
Therefore, what is desired is a method and a structure for controlling dopant outdiffusion from a highly doped region into the drain or source of a transistor structure in a DRAM that employs a buried strap structure during subsequent high temperature steps without compromising the integrity or the performance of the resultant DRAM.